1. Field of the Invention
This invention relates to the field of micro-device fabrication, and in particular to a method of a microstructure for use in the manufacture of MEMS (Micro-Electro-Mechanical-Systems) devices.
2. Description of Related Art
MEMS devices are becoming important in many applications. These devices mimic the functions of many mechanical devices on a microscopic scale. Typical examples of MEMS devices are micro-gyroscopes, micro-accelerometers, resonant accelerometers, micro-mirrors, micro-motors, micro-actuators micro optical switches. MEMS devices have at least one moving component to perform the mechanical function.
The manufacture of MEMS devices integrating at least one moving component typically requires the use of a stress-relieved polysilicon layer having a thickness range between 0.5 and about 40 μm. This must be precisely patterned with photoresist and precisely etched in a dry etcher capable of producing a vertical etch so as to achieve the required patterned stress-relieved polysilicon, which can be released from underlying sacrificial material. Unfortunately, a polysilicon layer of this thickness has a rough upper surface, which causes parasitic light scattering during photoresist exposure. This results in uncontrolled photoresist patterns and uncontrolled polysilicon patterns following polysilicon etch. To cope with this parasitic light scattering situation, chemical-mechanical-polishing (CMP), and/or photoresist etch-back (PEB) of the thick polysilicon layer have been used to reduce the surface roughness. Unfortunately, these two approaches are themselves associated with residual problems:
The CMP technique results in undesirable variations in the thickness of polysilicon over the underlying topology; requires a extra thicker polysilicon layer to be deposited in order to achieve the required nominal thickness after polishing, thus increasing cost; and requires costly equipment and consumables.
The PEB technique results in major undesirable variations in the thickness of polysilicon over the underlying topology; requires a thick polysilicon layer to be deposited in order to achieve the required nominal thickness following extensive photoresist etch-back, thus increasing processing cost; requires a thick, high-viscosity sacrificial photoresist to be coated and stabilized using a photoresist coater and other post-coating equipment; and requires the thick stabilized sacrificial photoresist to be etched-back at the same rate as the thicker-than-required polysilicon using an optimized etcher.
The polysilicon thickness variations and extra processing cost are undesirable for many of high precision and low-cost MEMS devices, particularly devices used for automotive applications, such as micro-accelerometers and micro-gyroscopes. These devices are very sensitive to polysilicon thickness since the sidewalls of the patterned thick polysilicon layer define electrodes of precision capacitors used for actuation and/or sensing elements.
The well characterised electrical, thermal, chemical and mechanical properties of silicon allow thick polysilicon to become the major building block of most MEMS devices manufactured today.
Thick polysilicon allows mechanical structures to be released from their underlying sacrificial material over large distances of the order of a few thousands of micrometers and suspended as millimeters-long micro-bridges acting as movement sensors for accelerometers or micro-gyros. An example of such a micro-gyro is described in U.S. Pat. No. 5,955,668 entitled ‘Multi-element micro-gyro’, which is herein incorporated by reference.
Unfortunately, polysilicon surface roughness increases rapidly with the deposited thickness of polysilicon and the resulting photoresist lithography is not without problems.
FIG. 1 shows the typical resulting surface roughness associated with various thicknesses of polysilicon deposited from the thermal decomposition of silane at 620° C. The surface roughness is measured by Atomic Force Microscopy (AFM). This shows that thicker polysilicon is associated with a rougher surface. Unfortunately, thicker polysilicon is also required for high performance MEMS devices.
Precision photoresist patterning is difficult on thick polysilicon because its rough surface is composed of a multitude of pyramids acting as micro-mirrors reflecting light in undesired directions.
FIG. 2 shows a typical three dimensional texture of the surface of an 11 μm thick polysilicon layer. This shows that this surface is covered by a series of pyramids of random height up to 1.5 μm or more.
Parasitic light reflection onto the surface of these randomly shaped pyramids causes undesirable randomly shaped photoresist patterns after exposure and development.
FIG. 3 shows the mechanism by which randomly shaped polysilicon lines are formed when photoresist is exposed over a thick polysilicon with a rough surface. It will be seen that the parasitic light reflection on the facets of the formed pyramids composing the rough surface of thick polysilicon layers of MEMS devices results in random photoresist lines and in random etched polysilicon lines. Two techniques have been developed to eliminate this photolithography problem in the fabrication of MEMS devices.
The first technique is disclosed in U.S. Pat. No. 5,937,275 entitled ‘Method of producing acceleration sensors’, the contents of which are herein incorporated by reference. This technique is shown in FIG. 4. A photoresist etch-back (PEB) process is used to eliminate the surface roughness of the thick polysilicon. The following sequence of steps must be carried out at least once and preferably twice so as to reduce the surface roughness of the thick deposited polysilicon layer sufficiently to produce controlled polysilicon patterns after an etch through the photoresist mask.                a) Deposit a thick polysilicon layer, resulting in a rough surface;        b) Coat with a thick photoresist layer, thus producing a smooth upper surface;        c) Etch-back the polysilicon at the same rate as the photoresist, thus reducing the surface roughness of the polysilicon;        d) Remove the photoresist.        
The second technique is disclosed in the following cited reference from Jeffry J. Sniegowski: ‘Chemical-mechanical polishing: enhancing the manufacturability of MEMS’, SPIE Micromachinng and Microfabrication '96 Symposium, vol. 2879, Austin, Tex., Oct. 14-15, 1996, also published in: ‘Multi-level polysilicon surface-micromachining technology, applications and issues’, ASME 1996 International Mechanical Engineering Congress and Exposition, Nov. 17-22, 1996, Atlanta, Ga.
This second technique, shown in FIG. 5, involves the chemical-mechanical polishing (CMP) of thick polysilicon layers to reduce their surface roughness and allow precision photolithography and patterning.
As FIG. 6 shows, the reduction of the surface roughness of the thick polysilicon by machining its top surface by either one of these two prior art techniques (PEB or CMP) results in several drawbacks. The machining of the rough surface of the thick polysilicon results in an important and undesirable thickness variation of the thick polysilicon over underlying and patterned polysilicon layers (A′<B′ in FIG. 6). This underlying topology is unavoidable in most cases because most MEMS devices incorporate underlying polysilicon patterns used as electrical interconnects or mechanical elements. This thickness variation has an undesirable major impact on MEMS devices design since varying the underlying layout results in a thickness variation of the thick polysilicon at locations where variations are not acceptable.
An extra thick layer of polysilicon must be deposited since its initial thickness (referred as A=B in FIG. 6) is substantially reduced to a much smaller final thickness (referred as A′<B′ in FIG. 6) following PEB or CMP.
PEB requires a thick sacrificial photoresist to be etched-back once and probably more then once at the same rate as the thicker-than-required polysilicon using an etcher optimized for this application in order to transfer the smooth profile of the surface of photoresist into the etched-back polysilicon. CMP requires complex processing.
The local variation of thick polysilicon thickness following PEB or CMP is particularly important in the regions where the machined thick polysilicon covers underlying topology such as patterned polysilicon layers and the like. Depending upon the thickness of these underlying polysilicon layers and on the specifics of the PEB or CMP techniques, the thickness variation can approach the nominal thickness of the layer itself.
These local thickness variations are unacceptable for many MEMS devices using capacitance actuation such as micro-gyros, optical switches, micro-motors, micro-actuators and many other MEMS devices using thick polysilicon as electrode or mechanical element.
An example of such a MEMS requiring a uniformly thick polysilicon is described in the U.S. Pat. No. 5,955,668 titled ‘Multi-element micro-gyro’, which is herein incorporated by reference. The oscillating micro-gyro described in this patent is shown in FIG. 7. It requires capacitive actuation of the oscillation and capacitive sensing of the orthogonal oscillation produced by the Coriolis effect arising in the event of a rotation of the micro-gyro. The capacitors used for oscillation actuation are formed by the combination of a fixed thick polysilicon excitation vertical electrode and of a released neighbouring thick polysilicon responding vertical electrode. The capacitance of the oscillating actuation capacitor is then related to the surface area (i.e. height) of these two neighbouring thick polysilicon electrodes and to the oscillating gap (i.e. spacing) between these two neighbouring thick polysilicon electrodes. Any variation of the local thickness of the thick polysilicon results in an undesirable variation in the capacitance value and in the device performance. Similarly, any variation of the thick polysilicon line widths and spacings resulting from the parasitic light reflection on its rough surface will result in undesirable variation in the gaps between these two electrodes.
The PEB and CMP techniques used to machine the upper surface of the thick polysilicon minimize the variations of the thick polysilicon line widths and spacings and thus ensure reproducible line widths and spacings of the etched polysilicon. Unfortunately, these techniques do not prevent the local variations of local thickness of the thick polysilicon and thus result in undesirable variations in the activation and sense capacitors and in undesirable variations in actuation performance.
The process described in U.S. Pat. No. 5,364,818 entitled ‘SOG with moisture resistant protective capping layer”, the contents of which are herein incorporated by reference, has been used to level polysilicon and aluminum alloys interconnects in dielectrics of CMOS and other semiconductor devices.